A memory having a large capacity serial access memory unit is known used as a memory device (semiconductor memory device) for reading image data to be transmitted to a graphics equipment such as a CRT and for writing processed image data. One of such memories is a dual port video RAM. This RAM has a dynamic random access memory (DRAM) unit and a serial access memory (SAM) unit both of which can be accessed asynchronously.
FIG. 1 is a schematic diagram showing such a conventional memory device (dual port video RAM). As shown in FIG. 1, this memory device has a RAM unit 10 and a SAM unit 11. The RAM unit 10 has a cell array 14 made of capacitors and transistors, sense amplifiers 13 for amplifying data of a cell selected from the cell array 14, and a column decoder 12 for connecting a selected one of the sense amplifiers 13 to a data output path. The SAM unit 11 has serial registers 15 for one-dimensionally holding a set of serially accessed data, and serial decoders 16 for sequentially accessing the serial registers. Although not shown in FIG. 1, the cell array 14 has a row decoder for selecting one of word lines. In the RAM and SAM units 10 and 11, data in a plurality of cells connected to one word line (not shown) sensed by the RAM unit 10 is transferred by a transfer gate TRG. When any one of word lines of the RAM unit 10 is accessed, data on the line can be transferred to the SAM unit 11.
FIG. 2 is a circuit diagram showing the details of a circuit portion of FIG. 1 corresponding to one bit. As shown in FIG. 2, one of word lines WL1, WL2, . . . is selected for reading data from the cell array 14. Data in the cell array 14 is outputted to bit lines BL/BL*. At the sense amplifier 13, control lines SAN/SAP are controlled to guide the data on data lines DQ/DQ*. The cell array 14 is connected to the SAM unit 11 via the transfer gates TRG. After the data on the bit lines BL/BL* is established, the transfer gate TRG is turned on so that the data is transferred to nodes RN/RN* of the SAM unit 11. Then, the data is read onto serial data lines SQ/SQ*.
The operation of the memory device will further be described. Consider that one of word lines WL1, WL2, . . . is selected by a row decoder (not shown). Data on a cell C1 is outputted to the bit line BL. The bit lines BL/BL* are being set to an intermediate level before data access. Therefore, the level of the bit line BL* is at a reference level. The levels at the bit lines BL/BL* are sensed and amplified by the sense amplifier 13, as the level at the control line SAN goes toward V.sub.ss and the level at the control line SAP goes toward V.sub.cc. One of the levels at the bit lines BL/BL* is therefore set to "1" and the other is set to "0." Under this condition, when the gate G1 of the column decoder 12 turns on, the data is outputted from the RAM unit 10 via the complementary data lines DQ/DQ*. After the data on the bit lines BL/BL* is established and the transfer gate TRG rises, the data is transferred to the serial register of the SAM unit 11. When the transfer gate TRG falls, the data is held. Thereafter, when the gate G2 is turned on by the serial decoder 16, the data is serially outputted from the SAM unit 11 via the serial data lines SQ/SQ*.
With the memory device constructed as above, as the capacity of the RAM unit 10 increases, the number of at least ones of word lines WL1, WL2, . . . and bit lines BL/BL* increases. As the number of cells of the cell array 14 connected to the word lines WL1, WL2, . . . and bit lines BL/BL* increases, current for charging/discharging one of sense amplifiers 13 also increases, in addition to an increased number of sense amplifiers 13. From this reason, consumption current per one sense operation by the RAM unit 10 increases. A number of such memory devices (video RAMs) constructed as above are used on one system. These memory devices are often activated at the same time. As a result, an increase in operation current is considerably great.
An example of conventional memory devices constructed while taking into consideration of the above circumstances is shown in FIG. 3. As shown in FIG. 3, RAM units 10A and 10B are connected to a SAM unit 11 via transfer gates TRG1 and TRG2. The RAM unit 10A is constructed of a cell array 14A, sense amplifiers 13A, and column decoders 12A. The RAM unit 10B is constructed of a cell array 14B, sense amplifiers 13B, and column decoders 12B. In contrast with the structure shown in FIG. 1, the RAM unit 10 of FIG. 1 is divided into the two RAM units 10A and 10B disposed on opposite sides of the SAM unit 11.
With such an arrangement, the length of a bit line is reduced by a half. Also, a charge/discharge current per one sense amplifier is reduced by a half. Namely, a sense operation is performed only for the circuit portion belonging to an accessed word line in the RAM unit 10A or 10B. Therefore, as compared with the device shown in FIG. 1, the total current of the RAM units 10A and 10B is halved. However, the RAM units 10A and 10B are required to have their own independent sense amplifiers 13A and 13B and column decoders 12A and 12B.
FIG. 4 is a circuit diagram showing the details of a circuit portion corresponding to one column of the SAM unit shown in FIG. 3. As shown in FIG. 4, the number of cells connected to bit lines is halved. The bit lines of the RAM units 10A and 10B are connected via the transfer gates TRG1 and TRG2 to serial nodes RN/RN* of the serial registers 15 of the SAM unit 11. It is important that the bit lines of the RAM units 10A and 10B belonging to the same column are connected together at the SAM unit 11. With this arrangement, it is possible for the single SAM unit 11 to read and write data from and to cells belonging to a desired word line of either the RAM unit 10A or 10B. Similar to the case of FIGS. 1 and 2, the serial decoder 16 allows serial access to the serial registers 15. It is obvious that data transfer between the RAM units 10A and 10B and the SAM unit 11 is performed when one of the transfer gates TRG1 and TRG2 on the side of data transfer is turned on.
The structure of a conventional memory device fabricated on an integrated semiconductor circuit will be discussed. Such a device requires two types of low resistance wiring materials. One wiring material is used for forming data transfer lines including word lines WL1, WL2, . . . data lines DQ/DQ*, and signal lines to the column decoder 12 and serial decoder 16. The other wiring material is used for forming bit lines, and lines (nodes RN/RN*) interconnecting the bit lines of the RAM units 10A and 10B via the serial registers 15. As these wiring materials, metal silicide (sheet resistance several ohms/.quadrature.) is practically used for lines associated with the bit lines, and A1 (sheet resistance up to 50 milli-ohms/.quadrature.) is used for lines associated with word lines. Lines of these two different wiring materials cannot be intersected on an integrated semiconductor integrated circuit unless they are formed on two different layers.
As discussed above, a conventional memory device can reduce an operation current by dividing a RAM into two RAM sections. However, if the capacity of memory increases, power consumption cannot be reduced further unless the RAM is divided into a larger number of RAM sections. In such a case, however, in order for a single RAM to read and write data from and to cells belonging to an optional word line of the RAM, all RAM sections are required to be connected to the single SAM unit. However, in practice, the RAM cannot be divided into more than two RAM sections as was conventional, because bit lines are required to be extended to and connected to transfer gates.